1. Field of the Invention
The present invention generally relates to PCI Express (PCIe) technology, and in particular a bus extension system and method for adapting PCIe technology to current and future computer systems.
2. Description of the Prior Art
U.S. Patent Application No. 2012/0033370 teaches an interface card of a bus extension system which connects a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board and an edge connector adapted for insertion into an expansion slot on a motherboard of the computer system, and transmits signals between the motherboard and the interface card. An interface port is configured to mate with a connector of the cable and a logic integrated circuit on the printed circuit board. The logic integrated circuit functionally connects the edge connector with the expansion slot in order to buffer and propagate clock and data signals there-between that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power there-through to a PCIe-compliant peripheral device connected to the interface card through the interface port.
PCIe, formerly known as 3r.sup.d generation I/O (3GIO), has replaced the former peripheral component interconnect (PCI) parallel multi-drop bus as the main interconnect within current computer systems. In contrast to PCI, PCIe uses multiple lanes in parallel for each link. Each link constitutes a serial point-to-point connection and includes differential pairs for sending and receiving data in full duplex mode.
The currently prevalent PCIe 2.x standard features 500 MB/sec bandwidth per differential pair. In a PCIe 8× configuration (eight lanes), this results in a maximum of 8 GBs data transfers using concurrent send and receive transactions. The bandwidth of each PCIe link may be linearly scaled by adding signal pairs into a multi-lane configuration that can be custom tailored to the target (peripheral) device. Likewise, a multi-lane link may be split into several different targets. The width of each link or sub-link is negotiated at the initialization of each peripheral. At the end-point, the data that can be viewed as a byte stream are assembled/disassembled into the different lanes by the physical layer.
Given the high bandwidth and flexibility of the PCIe as an interconnect, it appears an unnecessary limitation to confine target devices to the physical location of an expansion card that is inserted into a PCIe slot of a computer. Rather, given space constraints as well as power and thermal management concerns, it would be advantageous to have target devices moved away from the motherboard and provide a high speed data link (HSDL) via dedicated cabling between an adapter card and the peripheral target device.
Referring to FIG. 1 a prior art bus expansion system is capable of providing flexible configurations for connecting PCIe-compliant peripheral devices to a host computer system using a cable that connects the peripheral devices to a PCIe bus on a motherboard of the computer system. PCIe protocol allows for concurrent send and receive transfers over dedicated differential signaling pairs of wires in full duplex mode. PCIe signals are routed from a PCIe expansion slot on the motherboard through a PCIe interface (expansion) card via an edge connector of the interface card. The edge connector of the PCIe interface card typically uses a 4-lane interface, though interface configurations up to 16-lanes are possible. The bus expansion system is advantageously able to make use of standard and relatively low-cost cables and connectors that are mounted on an adapted circuit board so that the pin-out connectivity on the interface card and the peripheral device has a mirrored configuration.
Still referring to FIG. 1 the bus extension system 10 is used with a host computer 12 and includes an interface card 14 that has been installed within an enclosure 16 in the computer 12. The interface card 14 is connected with a cable 18 to one of any number of PCIe-compliant peripheral devices 20 that are compatible with PCIe technology. The peripheral device 20 is represented as including a Serial ATA (SATA)-based solid state drive (SSD) controller 21 for controlling four solid-state drives (SSDs) 22. The interface card 14 and cable 18 are configured to provide a high speed data link (HSDL) between the computer 12 and the peripheral device 20. The PCIe-compliant peripheral devices 20 may include NAND flash-based mass storage devices capable of interfacing with a PCIe bus through suitable logic. The peripheral devices 20 can be PCIe first generation or second generation or later compliant, preferably using at least a 5 gbps (PCIe 2.x compliant) data rate. A non-limiting example of a suitable logic is a four-port PCI-based SATA controller 21 that fans out into four SATA SSDs 22. The SATA SSDs 22 may include an array of NAND flash-based mass storage devices located at the back end of the logic. The SATA controller 21 serves as host bus adapter for the SATA SSDs 22 used as the permanent storage media. The PCIe signals can be converted into PCI-X signals with a converter 23, for example, using a Pericom P17C9X130PCI Express to PCI-X Reversible Bridge, which then connects to the SATA controller 21. Other mapping strategies and non-volatile memory technologies could be used. The PCIe interface card 14 may be equipped with either four interface ports 24 or a single interface port 24. Each interface card 14 includes a printed circuit board, a bracket for mounting the circuit board within the computer enclosure 16 and an edge connector configured to connect the interface card 14 with a PCIe expansion slot (not shown) on a motherboard 30 mounted within the enclosure 16. Alternatively the edge connector can be functionally connected to the PCIe expansion slot on the motherboard 30 through a PCIe riser card (not shown) within the enclosure 16. A female connector forms part of each interface port 24 on the interface cards 14. One end of the cable 18 and a male connector affixed thereto for connecting to the female connector of the interface card 14. The female connector and its complementary male connector are preferably compliant with Small Form Factor (SFF) committee specifications SFF-8086 (currently Rev 2.3) and SFF-8087 (currently Rev. 2.4), which specify what is generally known as the mini Serial Attached SCSI (SAS) form factor, including the form factor known as mini-SAS 4i (wide compact internal connector). As such, the term “mini-SAS” is used herein to define connectors that meet the SFF-8086 and SFF-8087 specifications, and particular example of which is the mini-SAS 4i form factor. Additionally, the cable 18 can be an SFF-8087 compliant internal straight termination cable. As such, the connectors 25 and 32 and the cable 18 can be referred to as mini-SAS connectors and cable, though it should be understood that other types of connectors and cables could be developed and for use with the invention that are compatible with PCIe technology. As mini-SAS connectors, each connector has up to four differential signaling pairs for both transmitting and receiving data, along with a differential reference clock signal pair, a fundamental reset and an I2C interface for serial clock and data. In the form of a mini-SAS cable, the cable 18 is configured to have a “backplane to controller” pinout to achieve complete crossover of all signals, in other words, all thirty-six signals of a mini-SAS 4i connectors cross over. The cable 18 should meet or exceed the electrical specifications defined in the SAS-1.1 or current standard, and typically will be limited to lengths of about 0.5 meter (about 20 inches). Notably, power is not transferred from the motherboard 30 to the peripheral devices 20 through the connectors 25 of the interface ports 24. Mini-SAS connectors and cables are known in the art and therefore, aside from the above, will not be discussed in any further details. The interconnection between the interface card 14 and the PCIe-compliant peripheral device 20 of FIG. 1 is made through an extension of the bus of the motherboard 30 using a flexible cable 18 that can be of a type that is commercially available (“off-the-shelf”) and conforms to existing industry standards. In the example given, the cable 18 is a standard mini-SAS 4i cable having male connectors at each end that are configured for mating with a female connector of the interface card 14 and a similar-configured female connector of a PCIe interface port 40 of the peripheral device 20. PCIe functionality and protocol can be maintained throughout the entire configuration so that the interconnection is completely transparent to the host computer 10. In other words, the host computer 10 does not know whether the peripheral devices 20 are connected through the cable 18 or plugged directly into the PCIe interface slot on the motherboard 30. Based on the configuration of the system 10 and cards 14 discussed above, the interface card 14 serves to connect the signal traces of the PCIe expansion slot on the motherboard 30 to the PCIe-compliant peripheral device 20, and in particular the control, data and clock signals transmitted between the motherboard 30 and the SSDs 22 controlled by the four-port SATA controller 21. The interface card 14 connects four PCIe lanes originating on the motherboard 30 to four PCIe lanes in the interface port 24, from where they are transferred through the cable 18 to the receiving port 40 on the peripheral device 20. On the interface card 14, possible signal attenuation and delays stemming from the use of the cable 18 can be compensated for by the use of an integrated PCIe re-driver integrated circuit (not shown) of a type known in the art. The four PCIe lanes are physically combined into a single HSDL channel formed by the cable 18, resulting in the PCIe signals being transmitted over the cable 18 in full duplex mode. The data traces can be routed through the re-driver IC, which acts as a transmit/receive amplifier.
The inventor hereby incorporates all of the above referenced patent into this specification.